A prior static random access memory (SRAM) comprises an array of SRAM cells. Each SRAM cell is capable of storing a logical value using a pair of cross coupled devices such as inverters. Pullup gates in the cross coupled devices usually prevent leakage currents in the cell from discharging the internal data storage nodes of the cell.
Such an SRAM is typically implemented on an integrated circuit die according to a process technology that forms semiconductor and metal structures onto the integrated circuit die. The semiconductor structures usually include diffusion regions and polysilicon structures for the transistors in the SRAM. The metal structures often provide electrical interconnection between the transistors and other devices in the SRAM.
Such an integrated circuit process technology typically forms a plurality of contacts within each SRAM cell. Such contacts include contacts formed involving metal interconnect structures, polysilicon structures, and the diffusion regions of the transistors of the SRAM cell.
Defects sometimes occur in the semiconductor and metal structures of an integrated circuit during such a manufacturing process. Such manufacturing defects can cause failures in the contacts in the SRAM cells or in the individual transistors in the SRAM cells. A symmetric defect impairs the performance of both of the cross coupled devices of the cell. A defective contact in a power supply line which normally supplies power to the entire memory cell is considered a symmetric defect since both cross coupled devices are left without power. On the other hand, an asymmetric defect normally impairs only one of the cross coupled devices. A defective pullup in one inverter is an example of an asymmetric defect.
Manufacturing quality testing procedures are provided to detect such defects in newly manufactured integrated circuits. During a common manufacturing quality test procedure, the integrated circuits are placed in a highly specialized integrated circuit tester. Such a tester usually tests an SRAM by writing a predetermined data pattern to the SRAM cells and then immediately reading the SRAM cells to verify the stored data pattern. If the data written to the SRAM does not match the data read from the SRAM, then the SRAM is usually deemed defective.
Unfortunately, such a test procedure typically does not detect manufacturing defects that cause data retention problems in the SRAM cells. That is, defects that only show up after a cell has retained data for a relatively long period of time. For example, an SRAM cell having a defective pullup transistor at an internal data storage node retains stored charge for only a short period of time. The charge stored at the storage nodes of such an SRAM cell usually discharges through the diffusion regions of the transistors of the SRAM cell. A defective pullup transistor usually cannot maintain the charge level at the storage node for a long time.
One prior method for detecting such data retention defects is to provide a tester delay interval long enough to allow such a defective SRAM cell to discharge. That is, to increase the delay interval between the write of the test data pattern to the SRAM and the subsequent read-verify of the SRAM. Unfortunately, such tester delays significantly increase the time required for testing each integrated circuit. Consequently, more integrated circuit testers are necessary to obtain a certain throughput of integrated circuits when a data retention test including such a delay interval is used. The increased need for the extremely expensive integrated circuit testers results in a great increase in manufacturing costs.
One technique to avoid this cost is to include an on chip testing circuit to stress each SRAM cell. One such circuit is disclosed in copending application 08/277,148 filed Jul. 19, 1994 entitled "Memory Circuit with Stress Circuitry for Detecting Defects" which is assigned to the present assignee. This copending application discloses a circuit which stresses a memory cell using a pulldown transistor coupled to each bit line of the memory cell.